1. Field of the Invention
The present invention relates to a memory device, and more particularly to a memory device having an address buffer circuit which reduces current consumption.
2. Description of the Prior Art
FIG. 1 is a block diagram illustrating a normal address buffer circuit used in a memory device (e.g., 512M SDRAM). In FIG. 1, a control signal (EN) is an enable signal for controlling the operation of input buffers 111 to 118.
As shown in FIG. 1, an address signal output from a memory controller (not shown) is applied to the input buffers 111 to 118 via address pins 101 to 108. Address signals AI<0> to AI<13>, BAI<0> and BAI<1> output from the input buffers are applied to the interior of the memory device. Herein, the address signals AI<0> to AI<13> are used as row addresses and/or column addresses, and the address signals BAI<0> and BAI<1> are used as bank address signals to select a bank of the memory device.
FIG. 1 shows the configuration of the address buffer circuit generally used for a 512M DDR2 SDRAM. With respect to the 512M DDR SDRAM, Joint Electron Device Engineering Council (JEDEC) standard specifications require an address configuration as shown in Table 1 below.
TABLE 1Configuration128 M × 464 M × 832 M × 16Bank addressBA0, BA1BA0, BA1BA0, BA1Auto prechargeA10A10A10Row addressA0~A13A0~A13A0~A12Column addressA0~A9, A11A0~A9A0~A9
Referring to Table 1, it can be understood that different row addresses and column addresses are used depending on the configuration of the 512M DDR2 SDRAM.
For example, when the 512M DDR2 SDRAM is used as the 128M×4 and the 64M×8, address signals A0 to A9 and A11 to A13 are used as row address signals. However, when the 512M DDR2 SDRAM is used as the 32M×16, address signals A0 to A9, A11 and A12 are used as row address signals.
Also, when the 512M DDR2 SDRAM is used as the 128M×4, address signals A0 to A9 and A11 are used as column address signals. However, when the 512M DDR2 SDRAM is used as the 64M×8 and the 32M×16, address signals A0 to A9 are used as column address signals.
As described above, depending on the configuration of the 512M DDR2 SDRAM, a specific address and an address input buffer corresponding to the specific address may not be used. In spite of such conditions, if the operations of the address input buffers 111 to 118 are uniformly determined by a control signal (EN), unnecessary consumption of current is caused by an unused address input buffer.
According to the prior art, as shown in FIG. 1, when the 512M DDR2 SDRAM is used as the 32M×16, a NAND gate element 10 is employed for disabling the operation of an address input buffer 116 unused in the configuration of the 32M×16.
However, the conventional address buffer circuit shown in FIG. 1 has a problem in that it does not provide a function of controlling address input buffers selectively according to the characteristics of each memory device presented in Table 1.